1. Field of the Invention
The present invention relates to a junction type field effect transistor used in a high frequency integrated circuits and a optoelectronic intergrated circuits and more particularly to a homojunction type and heterojunction field effect transistor of a self-aligned structure having a short gate length.
2. Information Disclosure Statement
Generally, in the manufacture of a junction field effect transistor, it has been known to that the manufacture of a PN junction below a gate is the most important technology.
The prior art methods for manufacturing the PN junction below the gate metal are as follows;
First, the method of diffusing a P type dopant into a N type channel layer;
Next, the method of implanting a P type dopant ion into a N type channel layer;
Next, the method of etching an undesired portion after growing an P type epitaxial layer on a N type channel layer.
However, in view that the length of the gate electrode must be short in the order to obtain large transconductance and high cut-off frequency, there are some problems in above mentioned prior art methods.
The method of manufacturing JFET by a diffusion and implantation is not reproducible since thickness control of a channel layer resulted in P dopant diffusion is difficult, and manufacture of JFET having a short gate below 1.about.2 .mu.m is difficult because of non-self-aligned structure.
When the junction forming technology by the P type epitaxial layer growth method is used, there is a problem in that the etching control is difficult and not reproducible, whereas the short gate length and self-aligned structure can be obtained.
Accordingly, it is an object of the present invention to solve above mentioned problems.
It is a purpose of the present invention to provide a method for manufacturing a junction field effect transistor in which the problem occurring in the manufacture of the junction field effect transistor of InP type materials having an electron saturation velocity higher than that of silicon or GaAs, that is, the problem of the restriction of the gate length, is eliminated. Further, a gate length shorter than the mask length is obtained and the source, drain and gate metal are evaporated by the self-align method, to thereby obtain a gate length 1 .mu.m or gate length shorter than 1 .mu.m without utilizing an electron beam apparatus with high cost or X-ray lithography apparatus.